The field of the invention is that of integrated circuit fabrication, in particular forming sublithographic structures.
In the field of integrated circuit processing, there is relentless pressure to shrink the dimensions of individual features such as lines or holes.
At any given time, the state of lithography has a minimum achievable dimension that is sufficiently reliable to be used commercially.
Workers in the art have constructed “sublithographic” features by fabricating a dummy pillar or block with vertical sides, depositing a sidewall of material on the vertical sides with a thickness less than the minimum ground rule that is available, then removing the pillar selective to the sidewall, thereby leaving the sidewall as a thin vertical member (often called a fin) having a width less than is possible to achieve using the standard lithographic groundrules.
The sidewall is selected for its ability to form a thin fin that is strong enough to survive the processing, not for its electrical properties. Accordingly, the fin is often used as a hardmask to pattern a lower layer that is not as durable, but has better electrical properties.
A conventional process of forming thin vertical fins in the prior art includes the following;    (1) Form a stack of the structure material that will form the fins (silicon), hardmask (oxide) and temporary or dummy layer (silicon);    (2) Etch temporary pillars in the dummy layer that will support the sidewalls;    (3) Deposit a conformal (nitride) spacer film over the dummy pillars having a thickness that will define the width of the final structures;    (4) Directionally etch the horizontal portions of the conformal spacer film, exposing the top of the dummy material and the hardmask;    (5) Planarize the common top surface of the dummy material and the sidewalls;    (6) Remove the dummy pillars, leaving the sidewalls;    (7) HF clean the oxide hardmask after silicon removal;    (8) Etch the hardmask, using the sidewalls as a mask;    (9) Directionally etch the structure layer, using the hardmask to define the final structure, thereby forming the fins.
The sequence according to the prior art is illustrated in relevant format in FIGS. 1–4, in which;
FIG. 1 shows a typical starting material comprising a wafer substrate 10 that, in this case, is an SOI wafer having buried oxide insulator (BOX) 15 above which there is a device layer 20, also referred to as the structure layer, that will contain the final sublithographic structure.
An oxide hardmask 30 has been thermally grown or deposited on the top of the structure layer. The sidewall image transfer process forms a sidewall of sublithographic thickness on a dummy pillar formed in a dummy layer 50 and transfers the image to the hardmask, thereby defining a sublithographic hard mask that can be used to define the structure in the structure layer.
Such a process is often used to define the fins for a FINFET, but can also be used for other structures such as capacitor plates.
FIG. 2 shows the result of defining the dummy pillars 55, in which the pillars have a width denoted by bracket 52 that defines the pitch between the sidewalls and therefore the structure pitch between the pairs of final structures that will be formed. When the dummy pillars are defined by a lithographic process, the smallest value of distance 52 will be set by the limit of current lithographic technology.
Bracket 54 denotes the pitch of adjacent pillars and will also have a lower limit set by the current ground rules. The distance between a final structure resulting from a right sidewall on the pillar on the left in FIG. 2 and a corresponding structure resulting from the left sidewall on the pillar on the right in FIG. 2 will be distance 54 minus distance 52.
When the dummy material is amorphous silicon, the pillars 55 may be defined by a reactive ion etch using CF4, CHF3, CH2F2, CH3F, O2, Ar chemistry.
FIG. 3 shows the result of depositing a conformal layer of nitride 60 in a conventional CVD process. The thickness of layer 60 on the sides of pillars 55 (the sidewall thickness) will define the width of the oxide hardmask and thus also define the width of the final structures.
FIG. 4 shows the result of a directional nitride spacer etch using CF4, CHF3, CH2F2, CH3F, O2, Ar chemistry that removes the horizontal components of film 60 as shown. FIG. 4 shows the result of an overetch at the top of the pillars 55 that is required to assure that the lower horizontal component of film 60 resting on the hardmask 30 has been removed. Prior art methods typically planarize the top surface of the pillars and the top surface of the sidewalls.
Circles 32 in FIG. 4 indicate areas where the hardmask film 30 has been damaged by the nitride spacer etch. These areas will etch faster in the etch that defines the hardmask than the areas underneath pillars 55 that are protected by the pillars during this etch. The result of this asymmetry is that the hardmask will not have a flat top (or vertical sides) but will have a slanting top where the damaged oxide was removed more quickly. That defect in the hardmask results in poor quality of definition in the final structures.
Typically, the spacer transfer etch that defines the hard mask using the nitride spacers as a mask is a directional RIE etch. Even though directional, that etch attacks the oxide laterally in the area 32, resulting in the tapered hard mask.
This approach has a number of problems, as would be expected of an attempt to produce a smaller dimension than can be reliably produced using standard techniques.
In particular, transferring the sidewall image to the hard mask layer has been subject to a problem that the etching step that defines the sidewall damages the hardmask layer slightly, compared with the portion of the hard mask layer that is protected by the pillar. When the sidewall image is transferred to the hardmask, there can be differential etching because of the previous differential damage. That differential etching, in turn, can produce a hardmask that is not symmetric and that, in turn, produces a fin that is not up to standard.
An additional problem is that standard technology requires at least one planarization step that is both expensive and prone to cause defects in the material.